The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically a semiconductor device comprising transistors having control gates and floating gate electrodes, and a method for fabricating the semiconductor device.
As a typical semiconductor memory is known DRAM (Dynamic Random Access Memory). DRAM is a semiconductor memory which stores 1-bit information in one memory cell comprising one MISFET and one capacitor. DRAM has the memory cells increasingly micronized and the capacity increased. However, semiconductor memories having larger capacities are expected.
As a semiconductor device which can have larger capacities, the flash memory is noted. The flash memory is suitable to have large capacities because one memory cell of the flash memory comprises one MISFET alone.
A conventional semiconductor device will be explained with reference to FIG. 28. FIG. 28 is a sectional view of the conventional semiconductor device.
As shown in FIG. 28, device isolation regions 212 are formed on the surface of a semiconductor substrate 210. A floating gate 220 is formed on the semiconductor substrate 210 with a gate insulation film 224 formed therebetween. A control gate electrode 218 is formed on the floating gate electrode 220 with an insulation film 221 formed therebetween. A sidewall insulation film 234 is formed on the side walls of the floating gate electrode 220 and the control gate electrode 218. A source/drain region 232 is formed in the semiconductor substrate 210 on both sides of the control gate electrode 218 and the floating gate electrode 220 with the sidewall insulation film 234 formed on the side walls thereof. Thus, the conventional flash memory, i.e., the conventional semiconductor device is constituted.
In such semiconductor device, carriers are injected into the floating gate electrode 220 to store information. When carriers are injected into the floating gate electrode 220, hot carriers are generated in the channel region between the source region 232 and the drain region 232 while a voltage is applied between the channel region and the control gate electrode 218. When the voltage is applied between the channel region and the control gate electrode 218, hot carriers are injected into the floating gate electrode 220. Thus, information is stored in the floating gate electrode 220.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. 2002-15587
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. Hei 5-55602
However, in the conventional semiconductor device, when memory transistors 240 are formed, the control gate electrodes 218 are stacked on the floating gate electrodes 220. Accordingly, transistors for peripheral part and a select part, and the memory transistors 240 must be formed by different fabrication processes. The fabrication steps are accordingly increased, which is a barrier to the cost reduction. The conventional semiconductor device, in which hot carriers are injected into the floating gate electrodes 220, has large current consumption.